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Data Sheet
Table 7. Pin Function Descriptions
ADV7800
Pin No.
1 to 14, 155 to 158, 161 to
Mnemonic
P0 to P29
Type 1
O
Description
Video Pixel Output Port. See Figure 7 for details on pin mapping.
169, 172 to 174
15, 79, 143, 170
16, 22, 35, 59, 77, 82, 138,
144, 160, 171, 176
17
18
19
DVDDIO
DGND
LLC
CS/HS_OUT
SFL/SYNC_OUT
P
GND
O
O
O
Digital Input/Output Supply Voltage (3.3 V).
Digital Ground.
Line-Locked Output Clock for the Pixel Data.
Horizontal Synchronization or Composite Synchronization Signal. This
signal can be selected while in SDP mode.
Subcarrier Frequency Lock. This pin contains a serial output stream, which
can be used to lock the subcarrier frequency when this decoder is con-
nected to any digital video encoder from Analog Devices, Inc. SYNC_OUT
is the sliced synchronization output signal available only in CP mode.
20
FLD_DE_OUT
O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin
can also be enabled as a data enable signal (DE) to allow direct connection
to a HDMI?/DVI Tx IC.
21
23, 36, 60, 76, 137, 159, 175
24 to 34, 39
37, 47, 61
38, 48, 62
40, 41
42
VS_OUT
DVDD
SDRAM_A0 to
SDRAM_A11
DVDDIO_SDRAM
DGND_SDRAM
SDRAM_BA1,
SDRAM_BA0
SDRAM_CS
O
P
O
P
GND
O
O
Vertical Synchronization Output Signal (SDP and CP modes).
Digital Core Supply Voltage (1.8 V).
Address Outputs. Interface to external RAM address lines. See Figure 7 for
details on pin mapping.
External Memory Interface Digital Input/Output Supply (2.5 V for DDR, or
3.3 V for SDR).
External Memory Interface Digital GND.
Bank Address Outputs. Interface to external RAM bank address lines.
SDRAM_CS is a chip select function that enables and disables the command
decoder on the RAM.
43
SDRAM_RAS
O
Row Addres s Select Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
44
SDRAM_CAS
O
Column Address Select Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
45
SDRAM_WE
O
Write Enabl e Output Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
46, 72
SDRAM_LDM,
SDRAM_UDM
O
Data Mask Output. Data is masked when DM is high, for write data to the
external RAM. LDM corresponds to the data on SDRAM_DQ0 to
SDRAM_DQ7, and UDM corresponds to the data on SDRAM_DQ8 to
SDRAM_DQ15.
49
SDRAM_LDQS
I/O
Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This
is an output with read data and an input with write data. It is edge aligned
with write data and centered in read data. SDRAM_ LDQS corresponds to
the data on SDRAM_DQ0 to SDRAM_DQ7.
50 to 57, 63 to 70
58
71
SDRAM_DQ0 to
SDRAM_DQ15
SDRAM_VREF
SDRAM_UDQS
I/O
P
I/O
Data Bus. Interface to external RAM 16-bit data bus. See Figure 7 for details
on pin mapping.
1.25 V reference for DDR SDRAM interface or 1.65 V for SDR SDRAM interface.
Upper Data Strobe Pin. Data strobe pins for the RAM interface. This is an
output with read data and an input with write data. It is edge aligned with
write data and centered in read data. SDRAM_UDQS corresponds to the
data on SDRAM_DQ8 to SDRAM_DQ16.
73, 74
75
78
SDRAM_CK,
SDRAM_CK
SDRAM_CKE
CLKIN
O
O
I
Differential Clock Output. All address and control output signals to the
RAM should be sampled on the positive edge of SDRAM_CK and on the
negative edge of SDRAM_CK.
Clock Enable. This pin is used to enable the clock signals of the external RAM.
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI/HDMI Rx IC) and also in digital CVBS
input mode.
Rev. C | Page 11 of 28
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